wv3hg264m72eeu-d7 may 2006 rev. 0 advanced* 1 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 1gb C 2x64mx72 ddr2 sdram unbuffered, w/pll, mini-dimm description the wv3hg264m72eeu is a 2x64mx72 double data rate ddr2 sdram high density module. this memory module consists of eighteen 64mx8 bit with 4 banks ddr2 synchronous drams in fbga packages, mounted on a 244-pin dimm fr4 substrate. * this product is under development, is not quali? ed or characterized and is subject to change without notice. note: consult factory for availability of: ? vendor source control options ? industrial temperature option features unbuffered 244-pin, dual in-line memory module (mini-dimm) fast data transfer rates: pc2-6400*, pcs-5300*, pc2-4200 and pc2-3200 utilizes 800*, 667*, 533 and 400 mb/s ddr2 sdram components v cc = v ccq = 1.8v 0.1v v ccspd = 1.7v to 3.6v differential data strobe (dqs, dqs#) option four-bit prefetch architecture programmable cas# latency (cl): 3, 4, 5* and 6* programmable burst: length (4, 8) on-die termination (odt) serial presence detect (spd) with eeprom jedec standard 1.8v i/o (sstk_18 compatible) gold (au) edge contacts dual rank rohs compliant package option ? 244 pin mini-dimm ? pcb C 30.00mm (1.181") typ operating frequencies pc2-3200 pc2-4200 pc2-5300* pc2-6400* clock speed 200mhz 266mhz 333mhz 400mhz cl-t rcd -t rp 3-3-3 4-4-4 5-5-5 6-6-6 *consult factory for availability.
wv3hg264m72eeu-d7 may 2006 rev. 0 advanced 2 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs pin names pin name function a0-a13 address inputs ba0,ba1 sdram bank address dq0-dq63 data input/output cb0-cb7 check bits dqs0-dqs8 data strobes dqs0#-dqs8# data strobes complement odt0, odt1 on-die termination control ck0,ck0# clock inputs, positive line cke0, cke1 clock enables cs0#, cs1# chip selects ras# row address strobe cas# column address strobe we# write enable dm (0-8) data masks v ccspd spd power v cc voltage supply v ccq i/o power v ss ground sa0-sa2 spd address sda spd data input/output scl spd clock input v ref input/output reference nc no connect pin configuration pin no. symbol pin no. symbol pin no. symbol pin no. symbol 1v ref 62 a4 123 v ss 184 v ccq 2v ss 63 v ccq 124 dq4 185 a3 3 dq0 64 a2 125 dq5 186 a1 4 dq1 65 v cc 126 v ss 187 v cc 5v ss 66 v ss 127 dm0 188 ck0 6dqs0#67 v ss 128 nc 189 ck0# 7 dqs0 68 nc 129 v ss 190 v cc 8v ss 69 v cc 130 dq6 191 a0 9 dq2 70 a10/ap 131 dq7 192 ba1 10 dq3 71 ba0 132 v ss 193 v cc 11 v ss 72 v cc 133 dq12 194 ras# 12 dq8 73 we# 134 dq13 195 v ccq 13 dq9 74 v ccq 135 v ss 196 cs0# 14 v ss 75 cas# 136 dm1 197 v ccq 15 dqs1# 76 v ccq 137 nc 198 odt0 16 dqs1 77 cs1# 138 v ss 199 a13 17 v ss 78 odt1 139 nc 200 v cc 18 nc 79 v ccq 140 nc 201 nc 19 nc 80 nc 141 v ss 202 v ss 20 v ss 81 v ss 142 dq14 203 dq36 21 dq10 82 dq32 143 dq15 204 dq37 22 dq11 83 dq33 144 v ss 205 v ss 23 v ss 84 v ss 145 dq20 206 dm4 24 dq16 85 dqs4# 146 dq21 207 nc 25 dq17 86 dqs4 147 v ss 208 v ss 26 v ss 87 v ss 148 dm2 209 dq38 27 dqs2# 88 dq34 149 nc 210 dq39 28 dqs2 89 dq35 150 v ss 211 v ss 29 v ss 90 v ss 151 dq22 212 dq44 30 dq18 91 dq40 152 dq23 213 dq45 31 dq19 92 dq41 153 v ss 214 v ss 32 v ss 93 v ss 154 dq28 215 dm5 33 dq24 94 dqs5# 155 dq29 216 nc 34 dq25 95 dqs5 156 v ss 217 v ss 35 v ss 96 v ss 157 dm3 218 dq46 36 dqs3# 97 dq42 158 nc 219 dq47 37 dqs3 98 dq43 159 v ss 220 v ss 38 v ss 99 v ss 160 dq30 221 dq52 39 dq26 100 dq48 161 dq31 222 dq53 40 dq27 101 dq49 162 v ss 223 v ss 41 v ss 102 v ss 163 cb4 224 nc 42 cb0 103 sa2 164 cb5 225 nc 43 cb1 104 nc 165 v ss 226 v ss 44 v ss 105 v ss 166 dm8 227 dm6 45 dqs8# 106 dqs6# 167 nc 228 nc 46 dqs8 107 dqs6 168 v ss 229 v ss 47 v ss 108 v ss 169 cb6 230 dq54 48 cb2 109 dq50 170 cb7 231 dq55 49 cb3 110 dq51 171 v ss 232 v ss 50 v ss 111 v ss 172 nc 233 dq60 51 nc 112 dq56 173 v ccq 234 dq61 52 v ccq 113 dq57 174 cke1 235 v ss 53 cke0 114 v ss 175 v cc 236 dm7 54 v cc 115 dqs7# 176 nc 237 nc 55 nc 116 dqs7 177 nc 238 v ss 56 nc 117 v ss 178 v ccq 239 dq62 57 v ccq 118 dq58 179 a12 240 dq63 58 a11 119 dq59 180 a9 241 v ss 59 a7 120 v ss 181 v cc 242 sda 60 v cc 121 sa0 182 a8 243 scl 61 a5 122 sa1 183 a6 244 v ccspd reset (pin 18) is connected to both oe of the pll and reset# of the register .
wv3hg264m72eeu-d7 may 2006 rev. 0 advanced 3 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs functional block diagram cs# dm/ rdqs cs1# cs0# dqs0 dqs0# dm0 dqs1 dqs1# dm1 dqs2 dqs2# dm2 dqs3 dqs3# dm3 dqs7 dqs7# dm7 dqs6 dqs6# dm6 dqs5 dqs5# dm5 dqs4 dqs4# dm4 dqs8 dqs8# dm8 dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# cs# dm/ rdqs dqs dqs# dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 cb0 cb1 cb2 cb3 cb4 cb5 cb6 cb7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 serial pd sa0 sa1 sa2 a0 wp a1 a2 sda scl v ccspd v cc/ v ccq vref v ss serial pd ddr2 sdrams ddr2 sdrams ddr2 sdrams cs1# ba0-ba1 a0-a13 ras# cas# we# cke0 cke1 cs1# : ddr2 sdrams ba0-ba1 : ddr2 sdrams a0-a13 : ddr2 sdrams ras# : ddr2 sdrams cas# : ddr2 sdrams we# : ddr2 sdrams cke0 : ddr2 sdrams cke1 : ddr2 sdrams odt0 odt1 odt0 : ddr2 sdrams odt1 : ddr2 sdrams cs0# cs0# : ddr2 sdrams pll ck ck# 120 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ddr2 sdram x 2 ck ck# note: all resistor values are 22 ohms 5% unless otherwise speci? ed.
wv3hg264m72eeu-d7 may 2006 rev. 0 advanced 4 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs dc operating conditions all voltages referenced to v ss parameter symbol min typical max unit notes supply voltage v cc 1.7 1.8 1.9 v 3 i/o reference voltage v ref 0.49 x v cc 0.50 x v cc 0.51 x v cc v1 i/o termination voltage v tt v ref -0.04 v ref v ref +0.04 v 2 spd supply voltage v ccspd 1.7 - 3.6 v notes: 1 v ref is expected to equal v cc/2 of the transmitting device and to track variations in the dc level of the same. peak-to-peak noise on v ref may not exceed +/-1 percent of the dc value. peak-to-peak ac noise on v ref may not exceed +/-2 percent of v ref . this measurement is to be taken at the nearest v ref bypass capacitor. 2. v tt is not applied directly to the device. v tt is a system supply for signal termination resistors, is expected to be set equal to v ref and must track variations in the dc level of v ref . 3. v ccq of all ic's are tied to v cc . absolute maximum ratings symbol parameter min max units v cc voltage on v cc pin relative to v ss -0.5 2.3 v v in , v out voltage on any pin relative to v ss -0.5 2.3 v t stg storage temperature -55 100 c i l input leakage current; any input 0v wv3hg264m72eeu-d7 may 2006 rev. 0 advanced 5 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs operating temperature condition parameter symbol rating units notes operating temperature (commercial) t oper 0c to 85c c 1, 2 notes: 1. operating temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, pl ease refer to jedec jesd51 .2 2. at 0 - 85c, operation temperature range, all dram speci? cation will be supported. input dc logic level all voltages referenced to v ss parameter symbol min max unit input high (logic 1 ) voltage v ih (dc) v ref + 0.125 v ref + 0.300 v input low (logic 0) voltage v il (dc) -0.300 v ref - 0.125 v input ac logic level all voltages referenced to v ss parameter symbol min max unit ac input high (logic 1 ) voltage ddr2-400 & ddr2-533 v ih (ac) v ref + 0.250 v ac input high (logic 1 ) voltage ddr2-667 v ih (ac) v ref + 0.200 v ac input low (logic 0) voltage ddr2-400 & ddr2-533 v il (ac) v ref - 0.250 v ac input low (logic 1 ) voltage ddr2-667 v il (ac) v ref - 0.200 v
wv3hg264m72eeu-d7 may 2006 rev. 0 advanced 6 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ddr2 i cc specifications and conditions includes ddr2 sdram components only; v cc = +1.8v0.1v symbol parameter condition 806 665 534 403 unit i cc0* operating one bank active- precharge; t ck = t ck(i cc ) ; t rc = t rc(i cc ) ; t ras = t ras min(i cc ) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 1,337 1,292 1,292 ma i cc1* operating one bank active- read- precharge; i out = 0ma; bl = 4; cl = cl(i cc ); t ck = t ck(i cc ) ; t rc = t rc(i cc ) ; t ras = t ras min(i cc ) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching; data pattern is same as i cc4w . tbd 1,272 1,227 1,227 ma i cc2p** precharge power- down current; all banks idle; t ck = t ck(i cc ) ; cke is low; other control and address bus inputs are stable; data bus inputs are floating tbd 444 444 444 ma i cc2q** precharge quite standby current; all banks idle; t ck = t ck(i cc ) ; cke is high; cs# is high; other control and address bus inputs are stable; data bus inputs are floating tbd 930 840 840 ma i cc2n** precharge standby current; all banks idle; t ck = t ck(i cc ) ; cke is high; cs# is high; other control and address bus inputs are stable; data bus inputs are switching tbd 1,020 930 930 ma i cc3p** active power- down current; all banks open; t ck = t ck(i cc ) , cke is low; other control and address bus inputs are stable; data bus inputs are floating fast pdn exit mrs(12) = 0 tbd 840 840 840 ma slow pdn exit mrs(12) = 1 tbd 516 516 516 ma i cc3n** active standby current; all banks open; t ck = t ck(i cc ) ; t rc = t rc(i cc ) ; t ras = t ras min(i cc ) ; cke is high, cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 1,290 1,200 1,200 ma i cc4w* operating burst write current; all banks open; continuous burst writes; bl = 4; cl = cl(i cc ); al = 0; t ck = t ck(i cc ) ; t rc = t rc(i cc ) ; t ras = t ras min(i cc ) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data bus inputs are switching tbd 1,632 1,452 1,362 ma i cc4r* operating burst read current; all banks open; continuous burst reads; tout = 0ma; bl = 4; cl = cl(i cc ); al = 0; t ck = t ck(i cc ) ; t rc = t rc(i cc ) ; t ras = t ras min(i cc ) ; cke is high, cs# is high between valid commands; address bus inputs are switching; data pattern is same as i cc4w . tbd 1,677 1,497 1,362 ma i cc5** burst auto refresh current; t ck = t ck(i cc ) ; refresh command at every t rc(i cc ) interval; cke is high; cs# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching tbd 3,000 2,820 2,820 ma i cc6** self refresh current; ck and ck# at 0v; cke < 0.2v; other control and address bus inputs are floating; data bus inputs are floating normal tbd 144 144 144 ma i cc7* operating bank interleave read current; all bank interleaving reads; i out = 0ma; bl = 4; cl = cl(i cc ); al = t rcd(i cc ) - 1*t ck(i cc ) ; t ck = t ck(i cc ) ; t rc = t rc(i cc ) ; t rrd = t rrd min(i cc ) = 1*t ck(i cc ) ; cke is high; cs# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching tbd 2,352 2,352 2,352 ma notes: i cc speci? cation is based on samsung components. other dram manufacturers speci? cation may be different. * value calculated as one module rank in this operating condition, and all other module ranks in i cc2p ( cke low) mode. ** value calculated re? ects all module ranks in this operating condition.
wv3hg264m72eeu-d7 may 2006 rev. 0 advanced 7 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters v cc = +1.8v 0.1v parameter symbol 806 665 534 403 unit min max min max min max min max clock clock cycle time cl=6 t ck (6) tbd tbd cl=5 t ck (5) tbd tbd 3000 8000 ----ps cl=4 t ck (4) tbd tbd 3750 8000 3,750 8,000 5,000 8,000 ps cl=3 t ck (3) tbd tbd 5000 8000 5,000 8,000 5,000 8,000 ps ck high-level width t ch tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck ck low-level width t cl tbd tbd 0.45 0.55 0.45 0.55 0.45 0.55 t ck half clock period t hp tbd tbd min(t ch , t cl) min (t ch , t cl ) min (t ch , t cl ) ps clock jitter t jit tbd tbd -125 125 -125 125 -125 125 ps data dq output access time from ck/ck# t ac tbd tbd -450 +450 -500 +500 -600 +600 ps data-out high impedance window from ck/ck# t hz tbd tbd t ac(max) t ac(max) t ac(max) ps data-out low-impedance window from ck/ck# t lz tbd tbd t ac(min) t ac(max) t ac(min) t ac(max) t ac(min) t ac(max) ps dq and dm input setup time relative to dqs t ds tbd tbd 100 100 150 dq and dm input hold time relative to dqs t dh tbd tbd 175 225 275 dq and dm input pulse width (for each input) t dipw tbd tbd 0.35 0.35 0.35 t ck data hold skew factor t qhs tbd tbd 340 400 450 ps dq-dqs hold, dqs to ? rst dq to go nonvalid, per access t qh tbd tbd t hp - t qhs t hp - t qhs t hp - t qhs ps data valid output window (dvw) t dvw tbd tbd t qh - t dqsq t qh - t dqsq t qh - t dqsq ns data strobe dqs input high pulse width t dqsh tbd tbd 0.35 0.35 0.35 t ck dqs input low pulse width t dqsl tbd tbd 0.35 0.35 0.35 t ck dqs output access time from ck/ck# t dqsck tbd tbd -400 +400 -450 +450 -500 +500 ps dqs falling edge to ck rising - setup time t dss tbd tbd 0.2 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh tbd tbd 0.2 0.2 0.2 t ck dqs-dq skew, dos to last dq valid, per group, per access t dqsq tbd tbd 240 300 350 ps dqs read preamble t rpre tbd tbd 0.9 1.1 0.9 1.1 0.9 1.1 t ck dqs read postamble t rpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck dqs write preamble setup time t wpres tbd tbd 000ps dqs write preamble t wpre tbd tbd 0.35 0.35 0.35 t ck dqs write postamble t wpst tbd tbd 0.4 0.6 0.4 0.6 0.4 0.6 t ck write command to ? rst dqs latching transition t dqss tbd tbd wl-0.25 wl+0.25 wl-0.25 wl+0.25 wl-0.25 wl+0.25 t ck ac speci? cation is based on samsung components. other dram manufacturers speci? cation may be different.
wv3hg264m72eeu-d7 may 2006 rev. 0 advanced 8 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs ac timing parameters (continued) v cc = +1.8v 0.1v parameter symbol 806 665 534 403 unit min max min max min max min max command and address address and control input pulse width for each input t ipw tbd tbd 0.6 0.6 0.6 t ck address and control input setup time t is tbd tbd 200 250 250 ps address and control input hold time t ih tbd tbd 275 375 475 ps cas# to cas# command delay t ccd tbd tbd 222ps active to active (same bank) command t rc tbd tbd 54 55 55 ns active bank a to active bank b command t rrd tbd tbd 7.5 7.5 7.5 ns active to read or write delay t rcd tbd tbd 15 15 15 ns four bank activate period t faw tbd tbd 37.5 37.5 37.5 37.5 37.5 37.5 ns active to precharge command t ras tbd tbd 45 70,000 45 70,000 45 70,000 ns internal read to precharge command delay t rtp tbd tbd 7.5 7.5 7.5 ns write recovery time t wr tbd tbd 15 15 15 ns auto precharge write recovery + precharge time t dal tbd tbd t wr + t rp t wr + t rp t wr + t rp ns internal write to read command delay t wtr tbd tbd 7.5 7.5 10 ns precharge command period t rp tbd tbd 15 15 15 ns precharge all command period t rpa tbd tbd t rp + t ck t rp + t ck t rp + t ck ns load mode command cycle time t mrd tbd tbd 222t ck cke low to ck, ck# uncertainty t delay tbd tbd t is+ t ck+ t ih t is+ t ck+ t ih t is+ t ck+ t ih ns self refresh refresh to active or refresh to refresh command interval t rfc tbd tbd 105 70,000 105 70,000 105 70,000 ns average periodic refresh interval t refi tbd tbd 7.8 7.8 7.8 ns exit self refresh to non-read command t xsnr tbd tbd t rfc(min) + 10 t rfc(min) + 10 t rfc(min) + 10 ns exit self refresh to read t xsrd tbd tbd 200 200 200 t ck exit self refresh timing reference t lsxr tbd tbd t is t is t is ps odt odt turn-on delay t aond tbd tbd 222222t ck odt turn-on t acn tbd tbd t ac(min) t ac(max) + 1000 t ac(min) t ac(max) + 1000 t ac(min) t ac(max) + 1000 ps odt turn-off delay t aofd tbd tbd 2.5 2.5 2.5 2.5 2.5 2.5 t ck odt turn-off t aof tbd tbd t ac(min) t ac(max) + 600 t ac(min) t ac(max) + 600 t ac(min) t ac(max) + 600 ps odt turn-on (power-down mode) t aonpd tbd tbd t ac(min) + 2000 2 x t ck + t ac(max) + 1000 t ac(min) + 2000 2 x t ck + t ac(max) + 1000 t ac(min) + 2000 2 x t ck + t ac(max) + 1000 ps odt turn-off (power-down mode) t aofpd tbd tbd t ac(min) + 2000 2 x t ck + t ac(max) + 1000 +1000 t ac(min) + 2000 2 x t ck + t ac(max) + 1000 +1000 t ac(min) + 2000 2 x t ck + t ac(max) + 1000 ps odt to power-down entry latency t anpd tbd tbd 333t ck odt power-down exit latency t axpd tbd tbd 888t ck power-down exit active power-down to read command, mr[bit12=0] t xard tbd tbd 222t ck exit active power-down to read command, mr[bit12=1] t xards tbd tbd 7-al 6-al 6-al t ck exit precharge power-down to any non-read command t xp tbd tbd 222t ck cke minimum high/low time t cke tbd tbd 333t ck ac speci? cation is based on samsung components. other dram manufacturers speci? cation may be different.
wv3hg264m72eeu-d7 may 2006 rev. 0 advanced 9 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs 3.3 (0.130) typ 82.15 (3.234) 81.15 (3.222) front view 30.15 (1.187) 29.85 (1.175) 20.0 (0.787) typ 10.0 (0.394) typ 1.0 (0.039) typ 4.10 (0.161) 3.90 (0.154) 2.10 (0.083) 1.90 (0.075) 0.50 (0.02) r 1.80 (0.071) d x2 6.0 (0.236) typ 2.0 (0.079) typ 78.0 (3.071) typ pin 1 pin 122 42.90 (1.689) typ back view 3.6 (0.142) typ detail a detail b 33.6 (1.323) typ 38.4 (1.512) typ 3.2 (0.126) typ pin 244 pin 123 tolerances: + /- 0.13 (0.005) unless otherwise specified. detail a 3.60 (0.142) full r 3.80 0.10 (0.150 0.004) 1.30 (0.051) 1.00 0.05 (0.039 0.002) 2.55 (0.100) detail b 0.450.03 (0.018 0.001) 0.60 typ (0.024)typ 0.25 (0.010) max 3.80 (0.150) max 1.10 (0.043) max package dimensions for d7 * all dimensions are in millimeters and (inches) ordering information for d7 part number clock speed/ data rate cas latency t rcd t rp height* wv3hg264m72eeu806d7xxg** 400mhz/800mb/s 6 6 6 3 0.00mm (1.181") typ wv3hg264m72eeu665d7xxg** 333mhz/667mb/s 5 5 5 3 0.00mm (1.181") typ wv3hg264m72eeu534d7xxg 266mhz/533mb/s 4 4 4 30.00mm (1.181") typ wv3hg264m72eeu403d7xg 200mhz/400mb/s 3 3 3 30.00mm (1.181") typ ** contact factory for availability. notes: ? rohs product. (g = rohs compliant) ? vendor speci? c part numbers are used to provide memory components source control. the place holder for this is shown as lo wer casex in the part numbers above and is to be replaced with the respective vendors code. consult factory for quali? ed sourcing options. (m = micron, s = samsung & consult factory for others) ? consult factory for availability of industrial temperature (-40c to 85c) option
wv3hg264m72eeu-d7 may 2006 rev. 0 advanced 10 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs part numbering guide wv 3 h g 2 64m 72 e e u xxx d7 x x g wedc memory (sdram) ddr 2 gold dual rank depth bus width component width (x8) 1.8v unbuffered speed (mb/s) package 244 pin industrial temp option (for commercial leave "blank" for industrial add "i") component vendor name (m = micron) (s = samsung) g = rohs compliant
wv3hg264m72eeu-d7 may 2006 rev. 0 advanced 11 white electronic designs corporation ? (602) 437-1520 ? www.wedc.com white electronic designs document title 1gb C 2x64mx72 ddr2 sdram unbuffered, w/pll, mini-dimm dram die options: ? samsung: c-die, will move to e-die q2'06 ? micron: u37y: b-die revision history rev # history release date status rev 0 created may 2006 advanced
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